1. Technical Field
The present invention relates to a process for reproducing data from a recording medium to which interleaved data is recorded, and to a process for recording data to such a medium. The invention also relates to an error-correcting process applied when reproducing data from the recording medium, and to an error-correcting coding process applied when recording data to the recording medium.
2. Related Art
Recently, some products for reproducing at high speed video data, documents, and other types of digital information recorded in optical disks such as DVD and CD media have become widely available. High density recording of digital information to the optical disk media makes read errors due to dust, disk scratches, and similar problems unavoidable during data reproduction. To compensate for this problem, error-correcting coding is applied to the recording medium such as the optical disk on recording, and error-correcting is applied on reproduction.
FIG. 13 shows a conventional disk drive for recording and reproducing an optical disk storing video information. During reproduction, the optical head 1201 of this optical disk drive scans the optical disk and a recording/reproducing circuit 1202 then binarizes the obtained information. A modulator/demodulator 1203 then demodulates the digital signal, an ECC processor 1204 applies error-correcting, and a video signal processor 1205 decompresses the data to generate the desired video information. During recording, the video signal processor 1205 compresses the video information, the ECC processor 1204 applies error-correcting coding, the modulator/demodulator 1203 modulates the error-correcting coded signal, and the recording/reproducing circuit 1202 converts the digital signal to an analog signal for recording by the optical head 1201 to the optical disk.
Operation of the ECC processor 1204 during reproduction is described next. FIG. 14 shows the internal configuration of the ECC processor 1204 shown in FIG. 13. Reproduction data decoded by the demodulator is written through an arbiter 52 to one ECC block in a DRAM 51. The data is then sent through the arbiter 52 to an ECC processor 53 for error calculation and error-correcting processing, the error-correcting result is then written back through the arbiter 52 to the user data in the DRAM 51, and the user data alone is then sent from the DRAM 51 through the arbiter 52 to the video signal processor.
Operation of the ECC processor 1204 during recording is described next. Data compressed by the video signal processor is written through the arbiter 52 to the DRAM 51 and then sent through the arbiter 52 to the ECC processor 53. After error-correcting coding by the ECC processor 53, parity is written through the arbiter 52 to the DRAM 51, and the recording data is then sent through the arbiter 52 to the modulator (See, for example, Reference 1).
The data is thus passed at least three times over the bus between the DRAM and the arbiter before data output from the demodulator is sent to the video signal processor and before data output from the video signal processor is sent to the modulator. That is, these three times are (1) from demodulator to DRAM, (2) from ECC processor to DRAM, and (3) from video signal processor to DRAM. Frequently accessing the DRAM bus is therefore a bottleneck to high speed reading and writing optical disks.
Furthermore, when data recorded with a disk format in which the recording direction (“data direction”) of data on the disk and the error-correcting code direction of the recorded data are different is read from the disk and buffered to the DRAM, the direction of the data on the disk and the DRAM address sequence will necessarily differ when the data is recorded to the memory so that the DRAM address sequence and the error-correcting code direction are the same. This means that when writing data from the modulator/demodulator to DRAM, or transferring data from DRAM to the modulator/demodulator, the data cannot be transferred continuously and must be sent in one-byte units, thereby degrading DRAM bus access performance. Furthermore, because data can only be sent one byte at a time, bus access cannot be improved even if the DRAM bus width is increased.
Conversely, if data is arranged to DRAM so that the DRAM address sequence is the same as the direction of the data on the disk, the direction of the error-correcting code is necessarily different from the DRAM address sequence. This again means that data cannot be transferred continuously and must be sent in one-byte units when transferring data from DRAM to the error-correcting processor, and bus access performance is again degraded.
Regarding the recording format to the optical disk, proposed is a new recording format for, for example, digitally recording HDTV broadcasts to a disk by interleaving a first error-correcting code with low redundancy and a second error-correcting code with greater error-correcting capacity, and alternating the synchronization code and error-correcting code (refer to, for example, Reference 2).
When reproducing data from a disk to which data is recorded with this recording format combining a robust error-correcting code and an error-correcting code with weaker error-correcting capability, an erasure pointer to the first error-correcting code is generated from error location information obtained in the error-correcting process using the more robust second error-correcting code and synchronization error information obtained from synchronization code detection. Then the first error-correcting code with weak error-correcting performance is error-corrected for erasure, thereby improving error-correcting capability and providing high reliability data reproduction.
<** Reference>
1. International Publication No. WO 99/31661, (see FIG. 21)
2. Japanese published patent application 2002-521789
One way to resolve the above-described deterioration in bus access performance is to provide a buffer memory large enough to store a complete ECC block between the modulator/demodulator and DRAM. All data in one ECC block is then first buffered to the memory for interleaving or deinterleaving. Buffer transfers are also executed using the maximum number of bytes allowed by the DRAM bus width. While this method avoids a drop in bus access performance, it requires enough memory to store a full ECC block, thus increasing the circuit area.
Furthermore, in a recording format alternately recording two different error-correcting codes and a synchronization code at known period, these error-correcting codes are recorded with a different interleave. The error location information of the second error-correcting code with higher error-correcting capability is obtained in the error-correcting process after deinterleaving the second error-correcting code. The error location information is thus obtained having codes arranged in the same order as the code sequence of the second error-correcting code. The synchronization error information is also obtained based on the synchronization code detection result, and is therefore also obtained in the recording sequence. The order of the erasure pointers for erasure-correcting the first error-correcting code must also be in the same order as the first error-correcting code. This means that the second error-correcting code error location information and synchronization error information cannot be used as is to generate the erasure pointers based on the locations of errors in the second error-correcting code and synchronization code errors because they are not in the same order.